Designers generally increase performance of integrated circuits by increasing the operating frequencies and by increasing the number of components, such as transistors, in the circuits. To keep the circuit sizes manageable, designers have reduced or scaled down the size of the circuit components so that larger numbers of devices fit within smaller per unit areas. Today it is not uncommon to find advanced computer system chips that contain millions, even billions, of transistors. This increased density, however, has created numerous problems. One problem is heat. Since individual electronic components, such as transistors, each generate minute quantities of heat when operating, increased numbers of such devices in the newer circuits naturally lead to increased quantities of heat. Another problem is power consumption. Again, since each electronic circuit component consumes a minute amount of power while operating, circuits with increased numbers of such circuit components generally consume larger quantities of power.
As mentioned, designers have increased performance by continually scaling the circuits using deeper and deeper submicron technologies, such as 90 nm and 65 nm technologies. They have also improved performance by increasing the clock speeds. They have reduced latencies by reducing the physical channel length of the circuit elements, reducing the voltage supplies for the elements, and reducing the threshold voltages of transistors. However, reduced threshold voltages and reduced channel lengths of transistors have resulted in higher sub-threshold leakage currents. Accordingly, sub-threshold leakage power, increased power consumption, and increased heat dissipation have rapidly become formidable challenges for integrated circuit designers. Moreover, with the increased use of portable electronic systems, reducing power consumption has become a paramount design concern. Power dissipation reduces battery life, decreases system performance, reduces system reliability, and increases system packaging costs.
Among the various types of integrated circuits, there have been many architectural and circuit level studies completed for static random access memory (SRAM) circuits. Some people have reduced leakage current for SRAM circuits by using a power-gating technique. In this method, circuit designers place a gated-ground n-type metal oxide semiconductor (n-MOS) between ground and SRAM cells to turn off the standby actions of the cache and to reduce leakage current. This method produces a problematic floating virtual ground node and causes the circuit to be more susceptible to noise, which can degrade the stability of the data stored in the memory cells.
Other recent techniques to reduce leakage current for the standby operation of cache are called dynamic Vt SRAM and Data Retention Gated-Ground-Cache (DRG-Cache). Dynamic Vt SRAM increases the threshold voltage by body biasing. However, this technique is relatively costly because of the twin well process. Plus, Vt SRAM has reliability problems. The DRG-Cache approach has problems as well. To retain data of cache in standby mode, DRG-Cache requires proper sizing of the gated-ground transistor and requires a sensitive threshold voltage level. The DRG-Cache approach also has a drawback when the cache is in standby mode. When in standby mode, the DRG-Cache technique cuts off the gated ground n-MOS, potentially destroying data written into the SRAM cells. Additionally, the DRG-Cache technique requires a larger decoder to provide sufficient power for driving an extra resistive-capacitive (RC) load for the gated-ground n-MOS.
Designers recently proposed yet another technique for leakage reduction, referred to as N-Controlled SRAM (NC-SRAM). This approach utilizes two extra power supplies for creating an alternating virtual ground that switches between low and high. A circuit according to this technique has the ability to store data when cache is in the standby mode, with the read-write access times not affected significantly. However, this technique seems to require additional power supply hardware and introduces leakage current between the power supply and ground, as well as the power loop in the power grid.
What are needed are alternative methods, circuit apparatuses, and techniques to reduce leakage current without making circuits more susceptible to noise, without unduly increasing fabrication costs, and without requiring large amounts of additional circuit hardware.